OUR ProductS

GP-GPU based on RPP architecture

R8-An innovation GP-GOU based on RPP chip architecture

  • The Reconfigurable Parallel Processor (RPP) architecture transfers programmability from the time domain to the space domain. Under the RPP architecture, instructions are distributed to different PEs, and data flows through the PEs sequence to realize the program’s execution in space.
  • RPP is suitable for programs with large amounts of data parallelism.
  • With the innovation of AzurEngine, our RPP architecture has improved efficiency to a whole new level.

Our Products

AzurEngine R8 chip

Reconfigurable Parallel Processor (RPP) architecture-The computing efficiency of the RPP chip is equivalent to ASIC (application specific integrated circuit), the chip power consumption is lower, and the software programming is more flexible and convenient.

The main parameters:

  • Performance up to 16 TFLOPS and 32 TOPS
  • Support 32 video codec 1080p@30fps
  • Compatible with CUDA drivers and runtime APIs
  • Support graph network
  • Support CUDA language
  • Support multiple interface protocols
  • Power consumption is less than 14W

AzurEngine R8 accelerator card

The high computing power density and low power consumption board cards launched for the compact and embedded demand market provide the industry with accelerator products that meet the performance and power consumption requirements.

The main parameters:

  • Performance up to 16 TFLOPS and 32 TOPS
  • Support 32-channel video codec 1080p@30fps
  • 16GB LPDDR4x
  • Compatible with CUDA drivers and runtime APIs
  • Support graph network
  • Support CUDA language
  • Support multiple interface protocols
  • PCIE3.0 x4  

AzurEngine R8 Edge Server

Facing edge computing, high computing power and low power consumption integrated hardware platform

The main parameters:

  • Performance up to 16 TFLOPS and 32 TOPS
  • Support 32-channel video codec 1080p@30fps
  • 16GB LPDDR4x
  • Compatible with CUDA drivers and runtime APIs
  • Support graph network
  • Support CUDA language
  • Support multiple interface protocols