Parallel computing chips with high versatility and high performance, become a leader
in the filed of parallel computing
Chips based on RPP architecture will better meet the high-performance
computing needs of various scenarios
The core team has more than fifteen years of professional R＆D experience in the
field of chip design and development
Parallel computing chips with high versatility and high performance, become a leader
in the filed of parallel computing
Chips based on RPP architecture will better meet the high-performance
computing needs of various scenarios
The core team has more than fifteen years of professional R＆D experience in the
field of chip design and development
Parallel computing chips with high versatility and high
performance, become a leader in the filed
of parallel computing
Chips based on RPP architecture will better meet the
high-performance computing needs of various scenarios
The core team has more than fifteen years of
professional R＆D experience in the
field of chip design and development
Our team
- It has attracted outstanding integrated circuit talents from various countries, and the chip team has an average of 15 years of experience in the industry.
- AzurEngine is led by international teams from the US and China with outstanding R&D and management experience， each core team member has more than 15 years of experiences.
Innovative chip architecture
- RPP is a novel processor architecture for computer vision applications, which combines the general processor’s programmability and ASIC’s power/cost efficiency together. With the unique architecture, the programmer can focus on the algorithm design without pay attention to the HW details.
Our vision
- Fill the gaps in the fast-developing high versatility and high-performance parallel computing chip field, and become a leader in the parallel computing industry.
ABOUT US
AzurEngine Technology Co., Ltd. was founded in Zhuhai City, Guangdong Province in 2017. We have developed a Reconfigurable Parallel Processor (RPP) architecture, which combines programmability and power efficiency together to bring powerful, efficient processors for parallel computing. We have amassed many international patents for the RPP architecture to develop an innovative GP-GPU.
We are focusing on the design and development of GP-GPU. RPP as an innovative chip architecture will be widely applied in the field of Parallel Computing which has numerous important applications such as video surveillance, industrial vision, autonomous vehicles, and so on.
Smaller and more powerful
Innovative RPP architecture will create high-efficiency, general-purpose and low-power GP-GPU chips
The chip area and power consumption of GPU are close to the limit, relying on the progress of the process technology RPP chip area and power consumption have great potential for improvement
Balance performance and versatility
Compared with the vector processor architecture, the RPP architecture will provide extremely high computational efficiency. Compared with the current mainstream GP-GPU,
The RPP innovative architecture will bring higher computing density and versatility close to GP-GPU, as well as efficiency comparable to professional chips
Core Products
In recent years, with the rapid development of AI technology, the demand for deep learning-based computer vision applications such as face recognition, car recognition, and logistics inspection has increased rapidly. Faced with the current and future requirements for chip computing power and programming flexibility With rapid growth, the market urgently needs powerful, flexible and low-power parallel computing chips.
GP-GPU chips based on the RPP (Reconfigurable Parallel Processor) architecture can effectively reduce chip costs while taking into account versatility and computing performance, and better meet the market’s long-term demand for chip products.
Application scenario
